1. Field of the Invention
The present invention relates to low power semiconductor memory circuits and methods. More specifically, the present invention relates to a reference voltage sub-system that allows fast power up after spending extended periods in an ultra-low power standby mode. The novel low reference voltage circuits and methods are suitable for use in low power microprocessors, microcontrollers, or power management devices.
2. Description of the Related Art
In general, in the descriptions that follow, the first occurrence of each special term of art that should be familiar to those skilled in the art of integrated circuits (“ICs”) and systems will be italicized. In addition, when a term that may be new or that may be used in a context that may be new, that term will be set forth in bold and at least one appropriate definition for that term will be provided. In addition, throughout this description, the terms assert and negate may be used when referring to the rendering of a signal, signal flag, status bit, or similar apparatus into its logically true or logically false state, respectively, and the term toggle to indicate the logical inversion of a signal from one logical state to the other. Alternatively, the mutually exclusive boolean states may be referred to as logic_0 and logic_1. Of course, as is well known, consistent system operation can be obtained by reversing the logic sense of all such signals, such that signals described herein as logically true become logically false and vice versa. Furthermore, it is of no relevance in such systems which specific voltage levels are selected to represent each of the logic states.
Hereinafter, reference to a facility shall mean a circuit or an associated set of circuits adapted to perform a particular function regardless of the physical layout of an embodiment thereof. Thus, the electronic elements comprising a given facility may be instantiated in the form of a hard macro adapted to be placed as a physically contiguous module, or in the form of a soft macro the elements of which may be distributed in any appropriate way that meets speed path requirements. In general, electronic systems comprise many different types of facilities, each adapted to perform specific functions in accordance with the intended capabilities of each system. Depending on the intended system application, the several facilities comprising the hardware platform may be integrated onto a single IC, or distributed across multiple ICs. Depending on cost and other known considerations, the electronic components, including the facility-instantiating IC(s), may be embodied in one or more single- or multi-chip packages. However, unless expressly stated to the contrary, the form of instantiation of any facility shall be considered as being purely a matter of design choice and not limiting to the scope of this disclosure.
Shown in FIG. 1 is a typical general-purpose computer system 100. Although not all of the electronic components illustrated in FIG. 1 may be operable in the sub-threshold or near-threshold domains in any particular embodiment, some, at least, may be advantageously adapted to do so, with concomitant reductions in system power dissipation. In particular, in recently-developed battery-powered mobile systems, such as smart-phones, tablets and the like, many of the discrete components typical of desktop or laptop devices illustrated in FIG. 1 are integrated into a single integrated circuit chip. Shown by way of example in FIG. 2 is a typical single-chip microcontroller unit (“MCU”) 200 comprising: a central processing unit (“CPU”), at least one reference voltage generator (“VREF”) facility 210, and at least one analog-to-digital converter (“ADC”) facility 220.
ADCs continually consume power during operation. As a result, ICs employing ADCs generally exhibit relatively high power consumption as a result of current drain when in use. Power reduction techniques help reduce power consumption, those power reduction techniques including powering down the ADC and associated ADC control circuits and ADC reference circuits when the ADC is not in use, i.e., in sleep mode.
FIG. 3 illustrates, in schematic form, a conventional reference voltage facility 300. Reference voltage facility 300 includes a VREF 302, reference buffer 304, feedback network 306, switch 308, ADC 310, reservoir capacitor 312. The VREF 302 may be a band-gap reference circuit, or any other suitable voltage reference circuit as would be understood by one of ordinary skill in the art. Reference buffer 304 is a conventional amplifier or buffer with the feedback network 306 determining the gain of the circuit as would be understood by one of ordinary skill in the art. Reference buffer 304 is adapted to receive a reference voltage from voltage reference generator 302 and to receive a feedback voltage from the feedback network 306. Reference buffer 304 outputs a stable reference voltage which is received by ADC 310 and reservoir capacitor 312.
During a sleep mode, or any other power reduction mode, reference buffer 304 is powered down using known techniques such as power gating. Powering down reference buffer 304 allows the top plate of capacitor 312 to float. As is known, excess leakage current will cause the stable reference voltage on the top plate of the capacitor to decrease over time. This reduction in voltage requires the reference buffer 304 to charge the stable reference voltage back to its pre-power down voltage level, thus delaying the conversion operations performed by the ADC 310.
Known systems have addressed the delay in restarting the ADC 310, utilizing capacitors along with sample and hold circuits and/or operations to maintain critical voltages such as the stable reference voltage required by ADC 310. However, these methods of maintaining a critical voltage has a finite time over which they are effective. Extended time spent in sleep mode or in a powered down mode results in the critical node voltages decreasing to a level that require an initial recharging of the critical node voltage, costing time and power consumption prior to achieving operation mode voltage levels.
In recent years, due to the growth of portable electronics, wearable technologies, and Internet of Things (IoT) technologies, there has been a push to lower the power consumption of devices. Additional time spent recharging the stable reference voltage to operable levels results in additional power draw by the system. What is needed is an apparatus or method where the stable reference voltage is held to a voltage during power down that is substantially the same as the voltage during operation.